1. Field of the Invention
The present invention relates to a complementary metal-oxide-semiconductor (CMOS) sensor. More particularly, the present invention relates to a correlated double sampling (CDS) circuit of a CMOS image sensor and a CMOS image sensor unit using the same.
2. Description of Related Art
With development of technology, digital cameras are widely used for freely recording images. The digital camera has a plurality of image sensor units for sensing images, which may transform optical signals into electronic signals and store the electronic signals in a memory card or other storage medium.
Referring to FIG. 1, FIG. 1 is a block diagram illustrating a conventional CMOS image sensor unit 10. The conventional image sensor unit 10 includes a timing generator 11, a row decoder 12, a column decoder 13, a pixel array 14, a correlated double sampling (CDS) circuit 15 and an analog signal processing (ASP) unit 16. Wherein, the ASP unit 16 includes a programmable gain amplifier (PGA) 160 and an analog-to-digital converter (ADC) 161.
The timing generator 11 is coupled to the row decoder 12, the column decoder 13 and the CDS circuit 15. The pixel array 14 is coupled to the row decoder 12 and the CDS circuit 15. The ASP unit 16 is coupled to the CDS circuit 15. The PGA 160 is coupled to an input terminal of the ASP unit 16 and the ADC 161, and the ADC 161 is coupled to an output terminal of the ASP unit 16.
The timing generator 11 generates a plurality of clock signals for controlling the row decoder 12, the column decoder 13 and the CDS circuit 15. The pixel array 14 senses optical signals based on an output of the row decoder 12, and transforms the optical signals into electronic signals. The CDS circuit 15 samples the electronic signals transformed by the pixel array 14 based on an output of the column decoder 13, and transmits sampling results to the ASP unit 16 for processing. The PGA 160 within the ASP unit 16 amplifies a voltage difference of the sampling results (the sampling results include levels of a reset signal and a sensed signal) according to a preset gain thereof, and transmits an amplified result to the ADC 161 to perform an analog-to-digital conversion, so as to generate a digital image signal.
According to the above description, during signal processing, the electronic signals output from the pixel array 14 are first stored in the CDS circuit 15, and then are sequentially read by the ASP unit 16. If an output signal of the pixel array 14 or an output signal of the CDS circuit 15 is mixed with noise, then it is hard for the rear ASP unit 16 to process. If the output signal of the pixel array 14 or the output signal of the CDS circuit 15 is too small, the PGA 160 then has to be set with a relatively great gain for compensation, which may lead to a design difficulty of the PGA 160 and the ADC 161. Therefore, noise influence to the output signals of the pixel array 14 and the CDS circuit 15 has to be reduced, and excessive low gains thereof have to be avoided.
The conventional CDS circuit 15 is generally formed by source follower amplifiers or buffers. Since a linear input range of the source follower amplifiers or the buffers is limited, which is generally limited within 0.5 volts to 1.5 volts, excessive high or excessive low output electronic signal of the pixel array 14 may cause a distortion of the output of the CDS circuit 15. When the image sensor unit 10 operates, the pixel array 14 sequentially outputs the level of the reset signal and the level of the sensed signal, and a difference of the two signals represents an actual image signal.
Generally, the CDS 15 includes two buffers (or source follower amplifiers) and a sampling capacitor for simultaneously storing the level of the reset signal and the level of the sensed signal. If the output signal of the pixel array 14 exceeds the linear input range of the CDS circuit 15, the image signal is then distorted. In the CDS circuit 15, considering a bandwidth or a frequency thereof, and considering the linear input range, the buffers (or the source follower amplifiers) are generally formed by single stage amplifiers or two-stage amplifiers.
U.S. Pat. No. 5,965,871 provides a plurality of the CDS circuits, but some of the CDS circuits provided thereof still have the problem of insufficient linear input range. Though other CDS circuits provided thereof solve the problem of insufficient linear input range, the gains of the buffers (the source follower amplifiers) thereof are decreased, which may lead to the design difficulty of the rear PGA and the ADC.
According to the U.S. Pat. No. 5,965,871, the linear input range of the CDS circuit is increased by applying a coupling capacitor. Moreover, a bias source is applied for reducing an unmatched problem of devices thereof. Since the coupling capacitor is applied, gains of the buffers (or the source follower amplifiers) thereof are decreased. Moreover, applying of the bias source may bring noises to the CDS circuit, and therefore the CDS circuits provided by the U.S. Pat. No. 5,965,871 are still required to be improved.
Moreover, the bias source has to provide biases to all the CDS circuits within the image sensor. If the bias source has the noise, performances of all the CDS circuits are influenced. In addition, since a distribution range of the CDS circuits within the image sensor is relatively great, it is a great challenge for providing a stable and accordant bias source.
In summary, increasing the linear input range of the conventional CDS may lead to decreasing of gains and increasing of circuit noises, and accordingly may lead to design difficulty of the rear circuits and deterioration of image quality thereof.